This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. P2002-062893, filed on Mar. 8, 2002; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device packaging technology, more specifically to a chip mounting substrate, a first level assembly using the chip mounting substrate, and a second level assembly using the first level assembly.
2. Description of the Related Art
The increase in density and the progress in large-scale integration have continued in semiconductor integrated circuits. Especially in DRAM, thin and small package such as ball grid array (BGA) package has been widely used. In a conventional BGA package, a plurality of connection electrodes are disposed in a lower surface of a rectangular-shaped mounting base, the substrate is defined by the lower surface and an upper surface opposite to the lower surface. The connection electrodes include: a power supply terminal to which a power supply potential is supplied; an ground terminal to which an ground potential is supplied; a selection signal input terminal to which a selection signal of a semiconductor chip is fed; an input and output terminal to which an input is fed or from which output signal is provided; an address terminal to which an address signal is fed; and the like. A chip mounting area is assigned on the upper surface of the mounting base. A semiconductor chip is fixed to the chip mounting area by using an adhesive or the like. Tape-shaped thin film is used as the mounting base.
Recently, high-density packaging is required in semiconductor packaging technology. The packaging area can be reduced by a configuration such that if conventional thin-type semiconductor packages are stacked. However, connection electrodes for superimposing the plurality of semiconductor packages are not provided in the thin-type semiconductor packages. Especially, in the case where plural packages using a BGA tape are stacked, it is not possible to superimpose the packages since the lands for connecting a lower level package with an upper level package are not provided. Therefore, it has been difficult to realize high-density packaging in thin-type semiconductor packages such as a BGA package.
A chip mounting substrate comprising: a mounting base defined by a first surface and a second surface opposite to the first surface; a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands; and a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands.
A first level assembly comprising: a mounting base defined by a first surface and a second surface opposite to the first surface; a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands; a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands; a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands; and a semiconductor chip mounted on a chip mounting area assigned adjacent to the second lands on the second surface.
A second level assembly comprising: a packaging board defined by a first surface assigning a substrate mounting area; a plurality of connection terminals disposed on the substrate mounting area; a plurality of signal terminals disposed around the substrate mounting area on the first surface of the packaging board; a plurality of signal wiring connected to the connection terminals and the signal terminals; a plurality of packaging balls disposed on the connection terminals, respectively; a mounting base disposed above the substrate mounting area, the mounting base being defined by a first surface and a second surface opposite to the first surface having a plurality of first lands disposed on the first surface, the first lands being classified into first and second groups of the first lands, a plurality of second lands disposed so as to face to the plurality of first lands on the second surface, the second lands being classified into first and second groups of the second lands, and a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands; and a semiconductor chip mounted on a chip mounting area assigned adjacent to the second lands on the second surface.